IEEE Based 2009 - 2010 - 2011 VLSI Projects

    SIMULATION & SYNTHESIS

  1. Design and Implementation of Area-optimized AES Based on FPGA
  2. Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Box
  3. High-performance FPGA Implementation of Discrete Wavelet Transform for Image Processing
  4. Design and FPGA Implementation of Modified Distributive Arithmetic Based DWT - IDWT Processor for Image Compression
  5. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder
  6. FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System
  7. Design and Implementation of an OFDM System for Vehicular Communications with FPGA Technologies
  8. VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems
  9. An Efficient Distributed Arithmetic based VLSI Architecture for DCT
  10. FPGA based FFT Algorithm Implementation in Wi-MAX Communications System
  11. Design of A Novel FSM based Reconfigurable Multimode Interleaver for WLAN Application
  12. Research on a Normal File Encryption and Decryption
  13. Efficient fault detection scheme for reliable AES architecture
  14. Design and Implementation of Area-optimized AES Based on FPGA
  15. Image Edge Detection Based on FPGA
  16. A FPGA Implementation of Low-Complexity Noise Removal
  17. FPGA Implementation of a Modular Active Noise Control System
  18. AREA optimized low power arithmetic and logic unit
  19. Design and FPGA Implementation of Modified Distributive Arithmetic Based DWT - IDW Processor for Image Compression
  20. New Reconfigurable Architectures for Implementing FIR Filters with Low Complexity
  21. An Efficient Viterbi Decoder for Digital Mobile Multimedia Broadcasting Receiver
  22. A high-performance pseudo-random number generator based on FPGA
  23. A FPGA Implementation Based on an Improved DES Algorithm
  24. Compact Designs of Sub Bytes and Mix Column for AES
  25. An efficient architecture for 2-D lifting-based discrete wavelet transforms
  26. Design of low power mixed radix FFT processor for MIMO OFDM systems
  27. High-Speed FPGA Implementation for DWT of Lifting Scheme
  28. Performance Analysis of Fast Adders Using VHDL
  29. The Design of Direct Digital Frequency Synthesis based on ROM Lookup Table
  30. A Novel Test Pattern Generator with High Fault Coverage for BIST Design
  31. Low-Transition Test Pattern Generation for BIST-Based Applications
  32. A Simple Digital VHDL QPSK Modulator Designed Using CPLD/FPGAs for Biomedical Devices Applications
  33. A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
  34. A Secure Spreader/Despreader for Code Division Multiple Access Applications
  35. Novel Multiplier less FPGA Implementation of CDMA 2000 Baseband Filter
  36. Implementation of an OFDM System Using FPGA
  37. Low-Transition Test Pattern Generation for BIST-Based Applications
  38. The Design of Image Edge Detection System Based on EDA Technique
  39. The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation
  40. An FPGA-based Architecture for Linear and Morphological Image Filtering
  41. Implementation and Performance Analysis of AES-128 CBC algorithm in WSNs
  42. The Design of Digital Frequency Transmission System Based on SOPC Technique
  43. An FPGA Implementation of Gradient Based Edge Detection Algorithm Design
  44. Efficient Sequential Architecture for the AES CCM Mode in the 802.16e Standard
  45. Scalable 128-bit AES-CM Crypto-Core Reconfigurable Implementation for Secure Communication
  46. Research on Image Median Filtering Algorithm and Its FPGA Implementation
  47. Implementation of an OFDM System Using FPGA
  48. Area Optimization of FIR Filter and its Implementation on FPGA
  49. FPGA IMPLEMENTATION OF FULLY PARALLEL FAST MDCT ALGORITHM
  50. High Speed Mixed Radix FFT/IFFT Pipelined Architecture for MIMO OFDM WLAN 802.11n
  51. Area Efficient TAM Controller and Wrapper Design for Embedded Cores
  52. Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
  53. A Pipelined Implementation of 802.11a transmission on reconfigurable platforms For Wireless LAN.
  54. Implementing and Optimizing a Direct Digital Frequency Synthesizer (DDFS) on FPGA
  55. An Area Efficient High Performance DCT Distributed Architecture for Video Compression.
  56. A BIST TPG for Low Power Dissipation and High Fault Coverage
  57. A Selective Trigger Scan Architecture for VLSI Testing.
  58. A New Scan Architecture for Both Low Power Testing and Test Volume Compression under SOC Test Environment
  59. Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design
  60. FPGA Realization of Lifting Based Forward Discrete Wavelet Transform for JPEG 2000
  61. Area efficient FIR filters for high speed FPGA implementation
  62. FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks
  63. A Novel Online Clock Skew Scheme for FPGA Based Asynchronous Wave-Pipelined Circuits
  64. Design and implementation of BPSK modulator and demodulator based on Modern DSP technology
  65. An Design of the 16-order FIR Digital Filter Based on FPGA

    66. FPGA IMPLEMENTATION

    WIRELESS COMMUNICATION

  66. RF Protocol Interface and Reconfigurable Logic Implementation for Low Power Wireless Application
  67. Design and Implementation of CDMA based Communication System in FPGA
  68. A Design of New Infrared Data Broadcasting Protocol for Wireless Communication
  69. Digital Design of DS-CDMA Transmitter and Receiver Using VHDL and FPGA
  70. High Performance, Low Cost FPGA Correlator for Wideband CDMA and Other Wireless Applications
  71. Hardware Implementation of QPSK Modulator for Satellite Communications
  72. Orthogonal Code Convolution Capabilities Using FPGA Implementation
  73. Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer
  74. Multi-architectural 128 bit AES-CBC Core based on Hardware AES Implementations for Secure Industrial Communications
  75. High Speed VLSI Design CCMP AES Cipher for WLAN (IEEE 802.11i)
  76. Design and Implementation of a Viterbi Decoder Using FPGAs

    77. CRYPTOGRAPHY

  77. A Low Cost Advanced Encryption Standard (AES) Co-Processor Implementation
  78. High Speed FPGA Architectures for the Data Encryption Standard
  79. An Area-Efficient Universal Cryptography Processor for Smart Cards
  80. A Novel Parity Bit Scheme for SBox in AES Circuits
  81. FPGA Implementation of AES Encryption and Decryption
  82. Implementations of High Throughput Sequential and Fully Pipelined AES Processors on FPGA
  83. The Design of a Low-Power Asynchronous DES Coprocessor for Sensor Network Encryption

    84. NETWORKING

  84. FPGA-based UDP/IP stacks parallelism for embedded Ethernet connectivity

    85. COMMUNICATION

  85. Design and Verification of Inter IC (I2C) bus controller
  86. Implementation of Phase Shift Keying (QPSK, BPSK)
  87. Implementations of Quadrature amplitude modulation technique
  88. Implementation of Frequency Shift Keying (BFSK, MFSK)
  89. UART Module for Real Time Application
  90. Speed, Area and Power Aspects of the Viterbi Decoder under Different ACS Structure

    91. CONTROLLER

  91. Bandwidth, Area Efficient and Target Device Independent SRAM Controller
  92. FPGA Implementation of SRAM memory Controller
  93. Speed and Direction control of Stepper Motor Using FPGA

    94. DSP – FILTERS

  94. Implementation of high-performance Finite Impulse response filters on FPGAs
  95. Implementation of high-performance infinite Impulse response filters on FPGA
  96. Improving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic
  97. Design of High Speed Decimation and Interpolation Filter
  98. An FIR Notch Filter for Adaptive Filtering of a Sinusoidal signal (Synthesis)
  99. An Efficient FPGA Implementation of a Pulse-Shaping IIR Filter
  100. An FPGA Implementation of the LMS Adaptive Filter for Audio Processing
  101. An Efficient FPGA Implementation of a Pulse-Shaping IIR Filter
  102. Design and implementation of multiplier less FIR Filter using Binary common Sub expression Algorithm
  103. Design a Minimized adder graph multiplier unit of FIR Filter for signal processing
  104. Design a Reduced slice graph multiplier unit of FIR Filter for software defined radio

    105. AUDIO PROCESSING

  105. Digital Frequency Synthesis implemented on a FPGA chip
  106. A Music Synthesizer on FPGA
  107. High speed Flash Audio Player for Multimedia Application
  108. FPGA Implementation of Karaoke Machine

    109. COMPRESSION

  109. Design and Implementation of a Lossless Parallel High-Speed Data Compression System
  110. Design and Implementation of Image compression using discrete cosine Transform
  111. Implementing High-Speed Search Applications using CAM

    112. IMAGE PROCESSING

  112. FPGA Realization of Forward Discrete Wavelet Transform for JPEG 2000
  113. Fast 2D-DCT Accelerator for FPGA-based SoCs
  114. Salt and Pepper Noise Removal Using 2D Median Filter for video processing on FPGA
  115. Area Efficient 2-DCT Architecture for H.264-AVC Video Compression Standard
  116. Design and implementation of Edge Detection algorithm for image pre-Processing
  117. Fpga Implementation of 2-D Median filter

    118. TESTING

  118. A BIST TPG for Low Power Dissipation and High Fault Coverage
  119. A New Scan Architecture for Both Low Power Testing and Test Volume Compression under SOC Test Environment
  120. A Selective Trigger Scan Architecture for VLSI Testing
  121. Optimization and Control of IEEE 1500 Wrappers and User Defined TAMs
  122. Fpga prototyping of a scan based design in an IEEE 1500 Wrapped core

    123. ALGORITHM AND ARCHITECTURE

  123. Design and Implementation of CORDIC core Algorithm in FPGA
  124. Design a Low Power Booth Multiplier in FPGA
  125. A Digit-Serial Multiplier for Finite Field GF (2m)
  126. Design a High Speed First-in First-out (FIFO) in FPGA
  127. Area Efficient Implementation of Programmable low power Multiplier for SRD Receiver
  128. Design and Implementation of Binary Common Sub-Expression algorithm for Resource Sharing multiplier

    129. APPLICATION PROJECTS

  129. Peripheral design using Picoblaze controller
  130. Zigbee based industrial automation
  131. Implementation of Memory interfacing using I2C in FPGA
  132. Implementation of Memory interfacing using SPI in FPGA
  133. Prepaid energy system for EB building
  134. Implementation of RTC using I2C in FPGA